{"created":"2024-10-09T10:31:18.837780+00:00","id":2001114,"links":{},"metadata":{"_buckets":{"deposit":"0c682a0f-55fd-4db2-8b13-df8e5056990c"},"_deposit":{"created_by":7,"id":"2001114","owners":[7],"pid":{"revision_id":0,"type":"depid","value":"2001114"},"status":"published"},"_oai":{"id":"oai:tokushima-u.repo.nii.ac.jp:02001114","sets":["1713829974766:1713854680413:1716363996082","1713853213384:1713853297799"]},"author_link":["93","86"],"item_10001_alternative_title_1":{"attribute_name":"タイトル別表記","attribute_value_mlt":[{"subitem_alternative_title":"On testing of open faults in multi-layered wiring LSIs","subitem_alternative_title_language":"en"}]},"item_10001_biblio_info_7":{"attribute_name":"bibliographic_information","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2008-05-30","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"20","bibliographicPageStart":"16","bibliographicVolumeNumber":"53","bibliographic_titles":[{"bibliographic_title":"徳島大学大学院ソシオテクノサイエンス研究部研究報告","bibliographic_titleLang":"ja"}]}]},"item_10001_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Open faults are difficult to test since the floating wire occurred by an open fault has unstable\nvoltage. In this work, the effect of adjacent lines around an open fault in multi-layered wiring LSIs\nis discussed. To observe the relation between an open fault and the adjacent lines, a 0.35μm CMOS\nIC is designed and fabricated. The open fault macros with a transmission gate and with an\nintentional break are included in the IC. The adjacent lines in the same layer and the different layers\nare placed in the test chip. The simulation and experimental results show that the voltage at the\nfloating wire is affected by the adjacent lines.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10001_source_id_9":{"attribute_name":"収録物ID","attribute_value_mlt":[{"subitem_source_identifier":"21859094","subitem_source_identifier_type":"ISSN"},{"subitem_source_identifier":"AA12214889","subitem_source_identifier_type":"NCID"}]},"item_10001_version_type_20":{"attribute_name":"出版タイプ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_1715043197608":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access"}]},"item_1723180141928":{"attribute_name":"item_1723180141928","attribute_value_mlt":[{"subitem_identifier_type":"URI","subitem_identifier_uri":"189147"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"四柳, 浩之","creatorNameLang":"ja"}],"nameIdentifiers":[{"nameIdentifier":"93","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"橋爪, 正樹","creatorNameLang":"ja"}],"nameIdentifiers":[{"nameIdentifier":"86","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_access","date":[{"dateType":"Available","dateValue":"2011-03-03"}],"displaytype":"detail","filename":"EID189147.pdf","filesize":[{"value":"1.93 MB"}],"format":"application/pdf","mimetype":"application/pdf","url":{"objectType":"fulltext","url":"https://tokushima-u.repo.nii.ac.jp/record/2001114/files/EID189147.pdf"},"version_id":"bc67cae5-8f28-401f-8c59-53abb06f9eef"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"testing","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"open faults","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"VLSI","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"multi-layered wiring","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"adjacent lines","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"item_resource_type","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"多層配線LSIの断線故障検査に関する研究","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"多層配線LSIの断線故障検査に関する研究","subitem_title_language":"ja"},{"subitem_title":"タソウ ハイセン LSI ノ ダンセン コショウ ケンサ ニ カンスル ケンキュウ","subitem_title_language":"ja-Kana"}]},"item_type_id":"40001","owner":"7","path":["1713853297799","1716363996082"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2011-03-03"},"publish_date":"2011-03-03","publish_status":"0","recid":"2001114","relation_version_is_last":true,"title":["多層配線LSIの断線故障検査に関する研究"],"weko_creator_id":"7","weko_shared_id":-1},"updated":"2024-10-09T10:31:27.094044+00:00"}